Dadda multiplier

The Dadda multiplier is a hardware binary multiplier design invented by computer scientist Luigi Dadda in 1965.^[1] It uses a selection of full and half adders to sum the partial products in stages (the Dadda tree or Dadda reduction) until two numbers are left. The design is similar to the Wallace multiplier, but the different reduction tree reduces the required number of gates (for all but the smallest operand sizes) and makes it slightly faster (for all operand sizes).^[2]

Dadda and Wallace multipliers have the same three steps for two bit strings ${\displaystyle w_{1}}$ and ${\displaystyle w_{2}}$ of lengths ${\displaystyle \ell _{1}}$ and ${\displaystyle \ell _{2}}$ respectively:

1. Multiply (logical AND) each bit of ${\displaystyle w_{1}}$, by each bit of ${\displaystyle w_{2}}$, yielding ${\displaystyle \ell _{1}\cdot \ell _{2}}$ results, grouped by weight in columns
2. Reduce the number of partial products by stages of full and half adders until we are left with at most two bits of each weight.
3. Add the final result with a conventional adder.

As with the Wallace multiplier, the multiplication products of the first step carry different weights reflecting the magnitude of the original bit values in the multiplication. For example, the product of bits ${\displaystyle a_{n}b_{m}}$ has weight ${\displaystyle n+m}$.

Unlike Wallace multipliers that reduce as much as possible on each layer, Dadda multipliers attempt to minimize the number of gates used, as well as input/output delay. Because of this, Dadda multipliers have a less expensive reduction phase, but the final numbers may be a few bits longer, thus requiring slightly bigger adders.