Explicitly parallel instruction computing

Explicitly parallel instruction computing (EPIC) is a term coined in 1997 by the HP–Intel alliance[1] to describe a computing paradigm that researchers had been investigating since the early 1980s.[2] This paradigm is also called Independence architectures. It was the basis for Intel and HP development of the Intel Itanium architecture,[3] and HP later asserted that "EPIC" was merely an old term for the Itanium architecture.[4] EPIC permits microprocessors to execute software instructions in parallel by using the compiler, rather than complex on-die circuitry, to control parallel instruction execution. This was intended to allow simple performance scaling without resorting to higher clock frequencies.

  1. ^ Schlansker and Rau (February 2000). "EPIC: An Architecture for Instruction-Level Parallel Processors" (PDF). HP Laboratories Palo Alto, HPL-1999-111. Retrieved 2008-05-08.
  2. ^ US 4847755, Morrison, Gordon E.; Brooks, Christopher B. & Gluck, Frederick G., "Parallel processing method and apparatus for increasing processing throughout by parallel processing low level instructions having natural concurrencies", published 1989-07-11, assigned to MCC Development Ltd. 
  3. ^ "Inventing Itanium: How HP Labs Helped Create the Next-Generation Chip Architecture". HP Labs. June 2001. Archived from the original on 2012-03-04. Retrieved 2007-12-14.
  4. ^ De Gelas, Johan (November 9, 2005). "Itanium–Is there light at the end of the tunnel?". AnandTech. Retrieved 2008-05-08.

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