The PA-7100LC is a microprocessor that implements the PA-RISC 1.1 instruction set architecture (ISA) developed by Hewlett-Packard (HP). It is also known as the PCX-L, and by its code-name, Hummingbird. It was designed as a low-cost microprocessor for low-end systems.[1] The first systems to feature the PA-7100LC were introduced in January 1994. These systems used 60 and 80 MHz clock rates. A 100 MHz part debuted in June 1994. The PA-7100LC was the first PA-RISC microprocessor to implement the MAX-1 multimedia instructions, an early single instruction, multiple data (SIMD) multimedia instruction set extension that provided instructions for improving the performance of MPEG video decoding.
The PA-7100LC was based on the PA-7100. Major improvements were improved superscalar execution and an extra integer unit. The PA-7100LC also implemented architectural improvements including the MAX-1 multimedia instructions, uncacheable memory pages, and bi-endian support. Superscalar execution was improved by adding the extra integer unit and modifying the control logic so that two integer instructions, two load–store unit operations, or an integer and a load or a store can be issued in one cycle in addition to the existing instruction combinations supported by the PA-7100.
A number of modifications were made to circuits derived from the PA-7100LC. Prominently, the floating-point unit multiplier was modified to take up less area by halving the tree of carry-save adders that summed the partial products of the mantissa. This simplification left the latency of single precision multiplies unchanged (two cycles), but increased the latency of double-precision multiplies to three cycles. The performance loss was deemed acceptable as the PA-7100LC was designed for mid-range multimedia workstations where single-precision multiplies are more prevalent. Integrated on-die to lower costs is a memory controller that supports up to 2 GB of memory and an I/O controller.
The organization of the caches is different from that of most HP-designed PA-RISC CPUs. The large external instruction and data caches have been replaced by an on-die instruction cache with a 1 KB capacity and a large external 8 KB to 2 MB cache. The external cache is unified, containing both instructions and data.[1]
The PA-7100LC consists of 900,000 transistors and measures 14.2 by 14.2 mm for an area of 201.64 mm2. It was fabricated by HP in their 0.8 μm three-level metal CMOS26B process. The PA-7100LC is packaged in a 432-pin ceramic pin grid array.