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RISC-V

RISC-V
DesignerUniversity of California, Berkeley
Bits32, 64, 128
Introduced6 August 2014 (2014-08-06)[1]
Version
  • unprivileged ISA 20191213,[2]
  • privileged ISA 20211203[3]
DesignRISC
TypeLoad–store
EncodingVariable
BranchingCompare-and-branch
EndiannessLittle[2]: 9 [a]
Page size4 KiB
Extensions
  • M: Multiplication
  • A: Atomics – LR/SC & fetch-and-op
  • F: Floating point (32-bit)
  • D: FP Double (64-bit)
  • Q: FP Quad (128-bit)
  • Zicsr: Control and status register support
  • Zifencei: Load/store fence
  • C: Compressed instructions (16-bit)
  • J: Interpreted or JIT-compiled languages support
OpenYes, royalty free
Registers
General-purpose
  • 16
  • 32
(Includes one always-zero register)
Floating point
  • 32
(Optional. Width depends on available extensions)

RISC-V[b] (pronounced "risk-five"[2]: 1 ) is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. Unlike most other ISA designs, RISC-V is provided under royalty-free open-source licenses. Many companies are offering or have announced RISC-V hardware; open source operating systems with RISC-V support are available, and the instruction set is supported in several popular software toolchains.

The project began in 2010 at the University of California, Berkeley. There are now members in over 70 countries contributing and collaborating to define RISC-V open specifications. RISC-V International, the non-profit managing RISC-V, is currently headquartered in Switzerland.[5][6]

The instruction set architecture (ISA) is licensed under the BSD License. In July 2023, RISC-V, in its 64-bit variant called riscv64,[7] was included as an official architecture of the major Linux distribution Debian in its unstable version.[8] The goal of this project was "to have Debian ready to install and run on systems implementing a variant of the RISC-V ISA."[9]

The conservative US think tank Jamestown Foundation believed in 2023 that China was set to dominate development of RISC-V because of the country's "concerns about dependency on American technology, which causes vulnerable 'chokepoints' [for the Chinese]."[10] Due to the strong research and development sector that was being promoted by the Chinese state, RISC-V was developing into a competitor to the chip architectures of both ARM and Intel.[10]

  1. ^ Asanović, Krste; Patterson, David A. (6 August 2014). Instruction Sets Should Be Free: The Case For RISC-V (PDF). EECS Department, University of California, Berkeley. UCB/EECS-2014-146.
  2. ^ a b c d Cite error: The named reference isa20191213 was invoked but never defined (see the help page).
  3. ^ Cite error: The named reference priv-isa was invoked but never defined (see the help page).
  4. ^ Urquhart, Roddy (29 March 2021). "What Does RISC-V Stand For? A brief history of the open ISA". Systems & Design: Opinion. Semiconductor Engineering.
  5. ^ "About RISC-V, RISC-V International is the global non-profit home of the open standard RISC-V Instruction Set Architecture (ISA)". RISC-V International.
  6. ^ "RISC-V To Move HQ to Switzerland Amid Trade War Concerns". EE Times Europe. 28 November 2019.
  7. ^ "RISC-V - Debian Wiki". wiki.debian.org. Retrieved 13 August 2024.
  8. ^ "riscv64 is now an official architecture". lists.debian.org. Retrieved 13 August 2024.
  9. ^ "RISC-V - Debian Wiki". wiki.debian.org. Retrieved 13 August 2024.
  10. ^ a b "Examining China's Grand Strategy For RISC-V". jamestown.org. Retrieved 13 August 2024.


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