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Designer | University of California, Berkeley |
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Bits | 32, 64, 128 |
Introduced | 6 August 2014[1] |
Version | |
Design | RISC |
Type | Load–store |
Encoding | Variable |
Branching | Compare-and-branch |
Endianness | Little[2]: 9 [a] |
Page size | 4 KiB |
Extensions |
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Open | Yes, royalty free |
Registers | |
General-purpose |
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Floating point |
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RISC-V[b] (pronounced "risk-five"[2]: 1 ) is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. Unlike most other ISA designs, RISC-V is provided under royalty-free open-source licenses. Many companies are offering or have announced RISC-V hardware; open source operating systems with RISC-V support are available, and the instruction set is supported in several popular software toolchains.
The project began in 2010 at the University of California, Berkeley. There are now members in over 70 countries contributing and collaborating to define RISC-V open specifications. RISC-V International, the non-profit managing RISC-V, is currently headquartered in Switzerland.[5][6]
The instruction set architecture (ISA) is licensed under the BSD License. In July 2023, RISC-V, in its 64-bit variant called riscv64,[7] was included as an official architecture of the major Linux distribution Debian in its unstable version.[8] The goal of this project was "to have Debian ready to install and run on systems implementing a variant of the RISC-V ISA."[9]
The conservative US think tank Jamestown Foundation believed in 2023 that China was set to dominate development of RISC-V because of the country's "concerns about dependency on American technology, which causes vulnerable 'chokepoints' [for the Chinese]."[10] Due to the strong research and development sector that was being promoted by the Chinese state, RISC-V was developing into a competitor to the chip architectures of both ARM and Intel.[10]
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